1. Field of the Invention
This invention relates to a semiconductor memory device, and in particular relates to a semiconductor memory device featuring high speed data reading realized by higher speed charging up of column lines.
2. Description of the Prior Art
Semiconductor memory devices include the non-volatile semiconductor memory device using as its memory devices MOS type field effect transistors (hereinafter "MOS FET") having double gate structure with a floating gate and a control gate.
FIG. 8 is a cross sectional view of such a MOS FET, and FIG. 9 shows its symbolized view. The MOS FET is provided with N-channel type source-drain diffusion layers 82 and 83 on a P-channel type substrate 81 and a floating gate 84 electrically insulated from outside and a control gate 85 for switching control both in an insulation layer (not shown) on the substrate. When the floating gate 84 is electrically neutral (hereinafter "non-write status"), the MOS FET becomes conductive under low control gate voltage (2 V, for example) as shown by 101 in FIG. 10. However, if high voltage (12.5 V, for example) is applied to the control gate 85 and the drain 83, electrons are supplied to the floating gate 84, which results in higher threshold voltage at memory devices seen from the control gate 85 (hereinafter called "write status"). In this case, the MOS FET becomes conductive only when high voltage (7 V, for example) as shown by 102 in FIG. 10 is applied to the control gate 85. Such a change in threshold voltage is utilized for data storage.
FIG. 6 is a schematic diagram to show the configuration of a conventional non-volatile semiconductor memory device using memory devices comprising MOS FETs as described above.
This semiconductor memory device has a memory array 40 comprising a plurality of column lines D1 to Dn connected to the drains of a plurality of memory devices MC11 to MCmn and a plurality of row lines SX1 to SXm serving as common gate electrodes for the memory devices on the column lines D1 to Dn.
The row lines SX1 to SXm control switching among memory devices according to row selection signals from a row decoder 41. The column lines D1 to Dn are connected to an input terminal SIN4 of a sensing circuit 44 via a column selection circuit 42 consisting of N-channel type MOS FETs MY1 to MYn, which are in turn controlled for switching according to column selection signals SY1 to SYn from a column decoder 43.
The sensing circuit 44 has its input terminal SIN4 connected with both the source of an N-channel type MOS FET MN41 and the input of an inverter circuit INV41, and the inverter circuit INV41 has its output VO4 connected with the gate of the above N-channel type MOS FET MN41. A P-channel type MOS FET MP41 serving as a load MOS FET has its source connected with the power supply VC and its gate and drain connected with the drain of the N-channel type MOS FET MN41. From the contact N400 where the gate and drain of the P-channel type MOS FET MP41 and the drain of the N-channel type MOS FET MN41 are connected, the output Vsa4 of the sensing circuit 44 is output.
A reference voltage generation circuit 45 has a configuration similar to the sensing circuit 44 with an N-channel type MOS FET MN42, an inverter circuit INV42 and a P-channel type MOS FET MP42. Input is provided to a reference memory device MCR4 equivalent to the memory devices MC11 to MCmn via an N-channel type MOS FET MYR4 equivalent to the N-channel type MOS FETs MY1 to MYn constituting the column selection circuit 42. The reference voltage generation circuit 45 generates reference voltage Vra4. A comparison amplifier 46 compares the output Vsa4 from the sensing circuit 44 with the output Vra4 from the reference voltage generation circuit 45 and outputs the result data output DAT4.
Now, the data reading operation is described. Suppose the memory device MC11 in the memory array 40 is selected.
If this selected memory device MC11 is in non-write status, the column line D1 and the input SIN4 of the sensing circuit 44 are discharged via the memory device MC11. This lowers the potential at the input SIN4 of the sensing circuit 44, which causes the output VO4 at the inverter circuit INV41 to have higher voltage and the N-channel type MOS FET MN41 to become conductive. Accordingly, the potential of the output Vsa4 from the sensing circuit 44 becomes low.
On the other hand, if the selected memory device MC11 is in write status, the column line D1 and the input SIN4 of the sensing circuit 44 are charged via the P-channel type MOS FET MP41 and the N-channel type MOS FET MN41. This increases the potential at the input SIN4 of the sensing circuit 44, causing the output VO4 at the inverter circuit INV41 to become low and the N-channel type MOS FET MN41 to become non-conductive. This results in high level output Vsa4 at the sensing circuit 44 under the effect of the P-channel type MOS FET MP41.
In the reference voltage generation circuit 45, the reference memory device MCR4 connected to its input RIN4 is in non-write status and its gate terminal connected to the power supply VC is conductive. Accordingly, the output Vra4 of the reference voltage generation circuit 45 is at low level as in the case of sensing circuit 44.
The output Vsa4 of the sensing circuit 44 thus changing depending on the status of the selected memory device is compared with the potential at the output Vra4 of the reference voltage generation circuit 45 by the comparison amplifier 46 so as to obtain the output DAT4 corresponding to the status of the selected memory device.
In a conventional semiconductor memory device, if a memory device in write status is selected, proper data is output only when the potential of the selected column line and the sensing circuit 44 are charged via the P-channel type MOS FET MP41 and the N-channel type MOS FET MN41, the output VO4 of the inverter circuit INV41 becomes low, the N-channel type MOS FET MN41 becomes non-conductive and the output Vsa4 of the sensing circuit 44 is brought to high level by the P-channel type MOS FET MP41.
For example, as shown by the voltage waveform in FIG. 7, if the column selection signals SY1 and SYn changes at the time T71 with shifting from the selection of a memory device in non-write status on the column line D1 to the selection of another memory device in write status on the column line Dn, the data output DAT4 is at high level during charging of the newly selected column line Dn (the period from the time T71 to T72) and becomes low upon completion of charging of the column line Dn (at T72). For this reason, when many memory devices are connected to each of the column lines D1 to Dn, causing large capacity to depend on the column lines, charging of the column lines D1 to Dn requires long time, which results in long time required for data reading.